1. Field of the Invention
The present invention relates to a synchronous word detection circuit, and in particular, to an improved synchronous word detection circuit which makes it possible to more easily detect a synchronous word by detecting a data start position of an input bit stream used for a multimedia system using an MPEG (Moving Picture Experts Group), detecting identical level bits from a bit stream inputted, and comparing the bits at a time.
2. Description of the Conventional Art
Generally, when transmitting in series a data in a bit stream form, a synchronous word having a predetermined value is carried on a start position of a data.
In addition, a decoder which decodes a data transmitted thereto in a bit stream form detects a synchronous word from the data transmitted in a bit stream form, thus converting the data into an original data.
In the conventional art, the value with respect to bit of the synchronous word is set a reference value, and then the data inputted is compared with the bit of the reference value.
FIG. 1 illustrates a conventional synchronous word detection circuit, and FIG. 2 illustrates a conventional synchronous word detection circuit.
As shown in FIG. 1, the conventional synchronous word detection circuit includes a serial/parallel converter 1 for outputting a parallel data by sequentially shifting a data serially inputted thereto a bit stream form in a state that a clock signal CLK is inputted thereto, and a one-to-one comparator 3 for receiving a data from the serial/parallel converter 1 and a reference value from a reference value generator 2 and applying a flag FG to the decoder when the parallel data and reference value are identical.
FIG. 2 illustrates a detailed configuration when the data of a synchronous word detected in the circuit of FIG. 1 is "1111 0000". As shown therein, in the serial/parallel converter 1, flip-flops FF1 through FF8 are connected in series in such a manner that the input terminal D of a first flip-flop FF1 receives a data transmitted thereto in a bit stream form, and the clock terminals CK of the flip-flops FF1 through FF8 receive a clock signal CLK, respectively.
In addition, in the one-to-one comparator 3, the output terminals Q of the flip-flops FF1 through FF8 are connected with input terminals of AND-gates AND1 through AND4 and OR-gates OR1 through OR4, and a reference value from the reference value generator 2 is inputted into other input terminals of the AND-gate AND1 through AND4 and the OR-gates OR1 through OR4, respectively. In addition, the output terminals of the AND-gates AND1 through AND4 and the OR-gates OR1 through OR4 are connected with the input terminals of a NOR-gate NOR1 and a NAND-gate NAND1, respectively, so that flag signals FG1 and FG2 are outputted from the output terminals of the NOR-gate NOR1 and the NAND-gate NAND1.
In the thusly constituted conventional synchronous word detection circuit, when a data is inputted in series in a bit stream form in a state that the clock signal CLK is inputted, the thusly inputted data are sequentially shifted through the flip-flops FF1 through FF8 of the serial/parallel converter 1 in accordance with a clock signal CLK, thus outputting a parallel data.
In addition, the data from the flip-flops FF1 through FF8 are transmitted to the input terminals of the AND-gates AND1 through AND2 and the OR-gates OR1 through OR4 of the one-to-one comparator 3, respectively, and the other input terminals of the AND-gates AND1 through AND4 and OR-gates OR1 through OR4 receive a reference value in accordance with the synchronous word from the reference value generator 2.
Assuming that the data of the synchronous word is configured in a form of "1111 0000", the reference value generator 2 outputs a synchronous word data of "1111 0000", and the thusly outputted data of "1111 0000" is transmitted to the other input terminals of the AND-gates AND1 through AND4 and the OR-gates OR1 through OR4.
When the synchronous word of "1111 0000" is inputted, the data of "1111 0000" are outputted from the output terminals Q of the flip-flops FF8 through FF1 of the serial/parallel converter 1, and then are transmitted to the input terminals of the OR-gates OR4 through OR1 and the AND-gates AND4 through AND1.
Thereafter, since the AND-gates AND1 through AND4 all output low level signals, and the OR-gates OR1 through OR4 all output high level signals, the NOR-gate NOR1 outputs a high level flag signals FG1, and the NAND-gate NAND1 outputs a low level flag signal FG2, thus judging that a predetermined data inputted is a synchronous word.
In addition, on the contrary, when another data except for the synchronous word is inputted, one of the AND-gates AND1 through AND4 outputs a high level signal, or one of the OR-gates OR1 through OR4 outputs a low level signal.
Therefore, the NOR-gate NOR1 outputs a low level signal or the NAND-gate NAND1 outputs a high level signal, so that it is judged that the data inputted is not a synchronous word.
However, in the conventional art, logic gates are used for each bit signal for comparing the bit signal of the synchronous word with a previously set reference value.
Therefore, in an MPEG I in which the synchronous word is configured in a form of "0X000001BA.sub.HEX " (where X denotes a predetermined value, and HEX denotes hexadecimal number), 32 logic gates are required for comparing the synchronous words by the bits. In addition, a transport stream of an MPEG II in which the synchronous word is configured in a form of "0X47.sub.HEX " needs 8 logic gates. Therefore, in the system for decoding the MPEG I and the MPEG II, 40 logic gates are needed. Therefore, many logic gates are disadvantageously used in the circuit, so that the construction of the circuit is complicated, and the fabrication cost is high. Furthermore, in other systems, the logic gages are required as many as the number of bits of the synchronous word, so that the construction is complicated, and the fabrication cost is high.